This is a common interview question at an early stage of your career and an important one too. So, let’s understand why we need a virtual interface in our environment. Interface signals are static ( Physically available ) in nature where the Class-based environment is dynamic in nature So, A virtual interface is a pointer to an actual interface in SystemVerilog. It is most often used in classes to provide a connection point to allow classes to access the signals in the interface through the virtual interface pointer dynamically
- Formal Verification: Where to use it and Why?
- Key Areas to consider during SOC Verification
- How to handle Interrupt in UVM?
- How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
- Clock Monitors in SoC Verification
- How UVM RAL works?
- Understanding with AXI Protocol and Cache Coherency