These are some of the best books to learn System Verilog, Fundamentals of Verification, Assertions as well as Functional Coverage.
- Writing Testbenches using SystemVerilog by Janick Bergeron – https://amzn.to/3FOU0pc
- SystemVerilog for Verification by Chris Spear – https://amzn.to/3UoN8mv
- Verilog and System Verilog Gotchas by Stuart Southerland – https://amzn.to/3sRYioe
- SystemVerilog Assertions Handbook: for Formal and Dynamic Verification By Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari – https://amzn.to/3Ucbjom
- Principles of Functional Verification by Andreas Meyer – https://amzn.to/3h70jue
- System Verilog Assertions and Functional Coverage – Guide to Language Methodology and Applications by Ashok B Mehta – https://amzn.to/3zF2GKW
- A Practical Guide for SystemVerilog Assertions by Srikanth Vijayaraghvan, Meyappan Ramanathan – https://amzn.to/3TXRlOm
- Introduction to SystemVerilog by Ashok B Mehta – https://amzn.to/3UiK8rW
- Getting Started with UVM: A Beginner’s Guide by Vanessa Cooper – https://amzn.to/3DvRMbS
- A Practical Guide to Adopting the Universal Verification Methodology (UVM) – https://amzn.to/3UqbufX
- The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology by Ray Salemi – https://amzn.to/3U2YVXU
- Practical UVM: Step by Step Examples – https://amzn.to/3WpQs2F
- Advanced UVM – https://amzn.to/3NxHOez
- Cracking Digital VLSI Verification Interview: Interview Success – https://amzn.to/3DYKkaG
- Writing Testbenches: Functional Verification of HDL Models – https://amzn.to/3FFPadW
- Formal Verification: An Essential Toolkit for Modern VLSI Design – https://amzn.to/3h1lLRb
- FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version by Pong P Chu – https://amzn.to/3zG0Qtu
- Fundamentals of Semiconductor Fabrication by S M SZE – https://amzn.to/3DwlddB
- Static Timing Analysis For Nanometer Design by J Bhaskar – https://amzn.to/3UjNn2u
- Constraining Design for Synthesis and Timing Analysis by Sridhar Gangadharan – https://amzn.to/3h9skRW
- Advance ASIC Chip Synthesis by Himanshu Bhatnagar – https://amzn.to/3Duyaot
- Physical Design Essentials by Khosrow Golshan – https://amzn.to/3WDnKf0
- Algorithm for VLSI Physical Design Automation by Naveed Sherwani – https://amzn.to/3Dwmcuj
- The Art of Timing Closure by Khosrow Golshan – https://amzn.to/3DAODaw
- Python for RTL Verification: A complete course in Python, cocotb, and pyuvm – https://amzn.to/3DXRqfo
- Doulos UVM Golden Reference Guide – https://amzn.to/3FCMFt3
- Logic Design and Verification Using SystemVerilog – https://amzn.to/3FKfzHB
- Finding Your Way Through Formal Verification – https://amzn.to/3FHRQYC
- VLSI Interview Questions with Answers – https://amzn.to/3DshiP4