How to handle Interrupt in UVM?
Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many […]
Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many […]
How to connect the DUT to the UVM Testbench?? In our traditional directed Testbench environments, all the components are “static” in
Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors
Today let’s talk about UVM RAL. In this post, I will introduce – What is RAL? and Why RAL is
As AXI protocol and Cache Coherency are commonly used concepts these days in almost each and every complex SoC’s so
Scoreboard The basic function of the scoreboard is to check the correctness of the output data of the design under
AGENTS As mentioned, an agent is a container that instantiates the driver, monitor, and sequencer. Agents can be either active
SEQUENCER The job of the sequencer is to control the flow of sequences to the driver. The fact that you
In earlier post i.e. https://theartofverification.com/uvm-testbench-architecture/ we learned which all components are required to develop UVM Environment/Testbench to verify complex Designs.
System Verilog assertions always help to speed up the verification process and it’s very powerful and widely used in the