The Art of Verification

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  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact

Tag - Verification

  • Assertions
  • Functional Coverage
  • Interview Questions
  • System Verilog
  • UVM

🔍 Beyond Design: Why Thought Process Unlocks Verification Excellence 🔍

May 12, 2023
by The Art of Verification
3 min read
2 Comments

🌟 Hello Fellow Verification Engineers! 🌟 Let’s talk about the secret sauce that fuels verification excellence – the power of our thought process! As experts in our field, we understand that practical approaches...

Continue reading

  • System Verilog
  • UVM

Importance of Stress Verification !!

April 19, 2023
by The Art of Verification
3 min read

In the world of semiconductor design and verification, the Universal Verification Methodology (UVM) has become the industry standard for coverage-driven verification (CDV). CDV aims to ensure that all parts of a design are...

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  • System Verilog
  • UVM

How to approach solving complex issues?

April 7, 2023
by The Art of Verification
3 min read

As an engineer, debugging complex issues can be one of the most challenging tasks we face on a daily basis. When a problem arises, it can be tempting to jump in and start looking for the solution right away. However, taking a...

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  • UVM

How to Verify Complex RISC-V–based Designs?

September 23, 2022
by The Art of Verification
5 min read

As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or...

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  • Assertions

Formal Verification: Where to use it and Why?

May 5, 2022
by The Art of Verification
12 min read

With innovations in technologies and methodology, the benefits of formal functional verification apply in many more areas. If we understand the characteristics of areas with high formal applicability, we can identify not only...

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  • UVM

How to handle Interrupt in UVM?

September 4, 2021
by The Art of Verification
7 min read

Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many IP blocks as part of it. In some way or other Interrupts are used to act as...

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  • UVM

How Virtual Interface can be pass using uvm_config_db in the UVM Environment?

September 2, 2021
by The Art of Verification
5 min read
7 Comments

How to connect the DUT to the UVM Testbench?? In our traditional directed Testbench environments, all the components are “static” in nature & information (data/control) is also exchanged in the form of...

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  • System Verilog
  • UVM

Clock Monitors in SoC Verification

August 5, 2021
by The Art of Verification
7 min read
6 Comments

Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors that use new bus architectures to communicate with them. They can also have various...

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  • UVM

How UVM RAL works?

July 5, 2021
by The Art of Verification
9 min read
12 Comments

Today let’s talk about UVM RAL. In this post, I will introduce – What is RAL? and Why RAL is needed? and How the UVM RAL structure looks like? We know that our DUT (be it an SoC or Subsystem or Design Block) contains a...

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  • Interview Questions

Understanding with AXI Protocol and Cache Coherency

June 24, 2021
by The Art of Verification
1 min read
15 Comments

As AXI protocol and Cache Coherency are commonly used concepts these days in almost each and every complex SoC’s so knowledge of those concepts are must for everyone to know how it works. All AXI and Cache...

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1 2 3 … 7 Next

Read More

  • Immediate Vs Concurrent Assertions
  • 🔍 Beyond Design: Why Thought Process Unlocks Verification Excellence 🔍
  • Semaphore in SystemVerilog:
  • “STATIC Properties and STATIC Methods”
  • UVM TLM Concepts:
  • Importance of Stress Verification !!
  • @event Vs wait(event.triggered) in SystemVerilog
  • How to Terminate UVM Test? (UVM Objections)
  • Constraint Override in System Verilog:
  • Reset Testing using Phase Jump in UVM
  • System Verilog rand_mode() and constraint_mode()
  • Inheritance in SystemVerilog OOPs:
  • UVM Phasing
  • Clock Monitors in SoC Verification
  • Shallow Copy Vs Deep Copy
  • M_sequencer Vs P_sequencer
  • Types of Coverage Metrics
  • Key Areas to consider during SOC Verification
  • Callbacks Vs Factory
  • Weighted Distribution in System Verilog
  • Understanding with AXI Protocol and Cache Coherency
  • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
  • How to handle Interrupt in UVM?
  • How UVM Callback works?
  • Concept of “This” in System Verilog:
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  • Home
  • About
  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact
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  • Twitter
  • Google Plus