Key Areas to consider during SOC Verification
Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore […]
Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore […]
The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of
Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many
How to connect the DUT to the UVM Testbench?? In our traditional directed Testbench environments, all the components are “static” in
Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors
Today let’s talk about UVM RAL. In this post, I will introduce – What is RAL? and Why RAL is
As AXI protocol and Cache Coherency are commonly used concepts these days in almost each and every complex SoC’s so
In the intricate world of ASIC Verification, the SOC Verification Flow is a cornerstone process that necessitates both expertise and experience. Many