Creative ways to solve problems
Before we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”. A wire is a data type that can model physical wires to connect two elements and It should only be driven by continuous assignment statement and cannot hold any value if not driven. “Reg” in Verilog […]
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Introduction In the world of ASIC Verification, understanding the intricacies of various programming constructs is paramount. Today, we’ll delve deep into the concept of STATIC properties and STATIC methods in SystemVerilog, their significance, and their practical applications. 1. When to Use STATIC Properties and STATIC Methods STATIC properties are particularly useful when we need to share data across all […]
Continue ReadingStatic: For a variable static lifetime is, its memory never de-allocated until simulation ends. Automatic: For a variable Automatic lifetime is, it is stack storage of variable (for multiple entries to a task, function, or block, it will have stack storage) and its memory will be de-allocated once execution of that method or block is […]
Continue ReadingThis is a common interview question at an early stage of your career and an important one too. So, let’s understand why we need a virtual interface in our environment. Interface signals are static ( Physically available ) in nature where the Class-based environment is dynamic in nature So, A virtual interface is a pointer […]
Continue ReadingPolymorphism is the ability to have the same code act differently based on the type of Object that its being working with. This is a key topic of any Object Oriented Programming language. SystemVerilog enables Polymorphism in two ways: Dynamic (Run-Time) Static (Compile-Time) Here we’ll discuss the Dynamic mode of Polymorphism which is supported via “Virtual […]
Continue ReadingBefore going towards Virtual and Pure Virtual methods let’s understand Virtual Class (Abstract Class) to make it more clear the understanding of exact concepts. Virtual Class (Abstract Class): Abstract class is nothing but a class that can be extended but cannot be instantiated. It’s the intention to be only a base class or prototype class. […]
Continue ReadingThe streaming operator uses the terminology pack when you take multiple variables and stream them into a single variable. And conversely, unpack is when you stream a single variable into multiple variables. Let’s understand through the below example:
Continue ReadingInheritance in SystemVerilog is the most commonly used principle of Object Oriented Programming (OOP) that facilitates reuse. It’s called Inheritance because it creates new classes taking all the existing Properties and Methods from the Base Class or Super Class. The new Class is called Extended Class or Derived Class. The Extended Class contains everything declared […]
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Coverage is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of constrained random testbenches. Types of coverage metrics – Let’s understand the types of coverage more deeply Code […]
Continue ReadingPlus args are command-line switches supported by the simulator. Usually, they are application-specific. As per SystemVerilog LRM arguments beginning with the ‘+’ character will be available using the $test$plusargs and $value$plusargs PLI APIs. Plus args are very useful in controlling many things in your environment like controlling your debug mode or setting a value like […]
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