As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or...
Tag - System Verilog
Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two...
The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of their SoCs. Quality is even more critical for highly configurable types of IP because...
As AXI protocol and Cache Coherency are commonly used concepts these days in almost each and every complex SoC’s so knowledge of those concepts are must for everyone to know how it works. All AXI and Cache...
Many people do not appreciate what makes a system-on-chip (SoC) different from other semiconductor devices. Many companies, especially in electronic design automation (EDA), toss around the term “SoC” without defining it or...
System Verilog assertions always help to speed up the verification process and it’s very powerful and widely used in the ASIC verification. Identifying the right set of checkers in the verification plan and implementing...
1. What is the difference between code coverage and functional coverage? There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification...
Verification Engineer is not just to write some test scenarios to verify something its a way beyond that. A verification engineer’s more focus after understanding of specifications are such as test planning, strategy need...
What is the difference between a reg, wire and logic in SystemVerilog? reg and wire are two data types that existed from Verilog, while logic is a new data type that was introduced in SystemVerilog. A wire is a data type...
Functional coverage and code coverage both are contributing highly on sign off criteria for verification. Implementers have to make sure that their test plan and test environment is intelligent enough to satisfy the...