Creative ways to solve problems
In the ever-evolving world of chip design, where circuits dance with logic and transistors tango with electrons, stands a breed of unsung heroes: the ASIC verification engineers. These digital detectives, armed with their arsenal of tests, hunt down bugs with the zeal of Indiana Jones and the precision of a Swiss watchmaker. Today, we delve […]
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In the realm of digital design, clock signals play a pivotal role in synchronizing the operations of various components. While clock division is a common approach for generating clock signals with different frequencies, an alternative method involves using a multiplied version of the reference clock. This blog post delves into the intricacies of handling clock […]
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Formal verification and functional verification are two complementary approaches to ASIC verification. Formal verification uses mathematical methods to prove that a design meets its specifications, while functional verification uses simulations to test the design against a variety of scenarios. Formal verification is more rigorous and can find bugs that functional verification may miss, but it […]
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As an experienced ASIC verification engineer, I’ve seen firsthand the importance of a thorough verification plan. A well-crafted verification plan can help to ensure that your design is bug-free and ready for production, while a poorly-crafted plan can lead to missed deadlines, costly rework, and even product recalls. In this blog post, I’ll discuss the […]
Continue ReadingScoreboard The basic function of the scoreboard is to check the correctness of the output data of the design under test. The scoreboard you create should derive from uvm_scoreboard; however, there is no current functionality of the uvm_scoreboard. You may be wondering why it’s important to mention if it doesn’t have any functionality at the […]
Continue Reading1. What is the difference between code coverage and functional coverage? There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification process. 1) Code Coverage: Code coverage is a metric used to measure the degree to which the design code (HDL model) is tested by […]
Continue ReadingFunctional coverage and code coverage both are contributing highly on sign off criteria for verification. Implementers have to make sure that their test plan and test environment is intelligent enough to satisfy the code/functional coverage closure. Code coverage is generated by tool with the help of the simulations generated by the test environment. So test […]
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Coverage is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of constrained random testbenches. Types of coverage metrics – Let’s understand the types of coverage more deeply Code […]
Continue ReadingFunctional Coverage is very important in Test Bench Development. It always gives us confidence in covered items listed on the verification plan. Usually, the goal of a verification engineer is to ensure that the design behaves correctly in its real environment according to specifications. Defining a coverage model is very important for any test bench […]
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