Streaming Operator in SystemVerilog(Pack/Unpack):

The streaming operator uses the terminology pack when you take multiple variables and stream them into a single variable. And conversely, unpack is when you stream a single variable into multiple variables.

Let’s understand through the below example:

class packet;
  bit [7:0] s_addr;
  bit [7:0] d_addr;
  bit [7:0] d_length;
  bit [7:0] crc;
  function void pack(ref bit [31:0] bytes[$]);
    bytes = { >> {s_addr, d_addr, d_length, crc}};
  endfunction : pack
  function void unpack(ref bit [31:0] bytes[$], ref packet pkt);
    { >> {pkt.s_addr, pkt.d_addr, pkt.d_length, pkt.crc}} = bytes;
  endfunction : unpack
endclass : packet
program main;
  packet pkt;
  packet pkt_1;
  bit [31:0] bytes[$];
  initial begin
    pkt = new();
    pkt.s_addr   = 8'h8C;
    pkt.d_addr   = 8'h00;
    pkt.d_length = 8'hA4;
    pkt.crc      = 8'hFF;
    void '(pkt.pack (bytes));
    foreach (bytes[i])
      $display("PACK: bytes[%0d]=%0h", i, bytes[i]);
    pkt_1 = new();
    pkt.unpack(bytes, pkt_1);
    $display("UNPACK : s_addr=%h, d_addr=%h, d_length=%h, crc=%h", pkt_1.s_addr, pkt_1.d_addr, pkt_1.d_length, pkt_1.crc);
endprogram : main

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The Art of Verification

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