Logic in Systemverilog:

Before we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”. 

A wire is a data type that can model physical wires to connect two elements and It should only be driven by continuous assignment statement and cannot hold any value if not driven.  

“Reg” in Verilog is a data type that holds its value and need to be driven from one procedural statement to next. 

In System Verilog, a variable declared with the logic data type cannot resolve multiple drivers. Variables can only have one continuous driver and It is 4 state (1, 0, X, Z) System Verilog data type. So, If we want to model uninitialized and unknown states (x and z) we will need to use a logic variable – mostly in RTL design as well as verification components like drivers/monitors/checkers that interface on a pin level

Let’s take an example to understand the usage of logic data type

module sv_logic (input logic xyz);
   parameter CYCLE;
   logic a, b, c;
initial begin
   a = 0;
   forever #(CYCLE/2) a = ~a
end

assign c = ~c;

endmodule

In above example, we can see statement “a = 0” is procedural assignment while statement “assign c = ~c” is a continuous assignment. So the important point to understand here is “SV allowed continuous assignments to logic variables, whereas in Verilog, you can’t use continuous assignments to”reg “ variables”I hope you understood the logic behind SystemVerilog “Logic”

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The Art of Verification

Hi, I’m Hardik, and welcome to The Art of Verification.

I’m a Verification Engineer who loves to crack complex designs and here to help others commit to mastering Verification Skills through self-learning, System Verilog, UVM, and most important to develop that thought process that every verification engineer should have.

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