How UVM Phasing is triggered?

To start a UVM Testbench, the run_test() method has to be called from the static part of the Testbench i.e called from an initial block in the top module of the Testbench.

module axi_top;

  axi_interface intf();                         // interface instance


  axi_slave_dut dut()                            // dut instance
  …
  ...                       
  ...

  initial begin
    uvm_config_db#(virtual axi_interface)::set(uvm_root::get(), "*", "intf", intf); // sets physical interface in uvm config database
    run_test("axi_test");
  end
  
  ...
  ...
  ...

endmodule

Once the run_test() method is called, it constructs the root component of the UVM environment & then triggers the UVM Phasing process. The run_test() method can be passed with a string argument, which in the above code is “axi_test”, to define the default type name which is used as the root node of the Testbench Hierarchy.

In addition, run_test() method also checks for a command line plusarg called UVM_TESTNAME and uses that plusarg string to lookup a factory registered uvm_component to override any default type name.

Hence to execute the “axi_test” using command line plusarg, we’ve to use the following command line:

% <simulator executable> +UVM_TESTNAME=axi_test

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The Art of Verification

Hi, I’m Hardik, and welcome to The Art of Verification.

I’m a Verification Engineer who loves to crack complex designs and here to help others commit to mastering Verification Skills through self-learning, System Verilog, UVM, and most important to develop that thought process that every verification engineer should have.

I’ve made it my mission to give back and serve others beyond myself.

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