Functional Coverage Options in System Verilog

Functional Coverage is very important in Test Bench Development. It always gives us confidence in covered items listed on the verification plan. Usually, the goal of a verification engineer is to ensure that the design behaves correctly in its real environment according to specifications.

Defining a coverage model is very important for any test bench development to get enough confidence in design verification.

Here I would like to share some of the important features of SystemVerilog Functional Coverage which helps users during verification activity.

Coverage Options available in System Verilog through which you can specify additional information in the cover group using provided options

1. Cover Group Comment – ‘option.comment’

You can add a comment to the coverage report to make them easier while analyzing:

covergroup CoverComment ;
  option.comment = "Register Definition section 1.1";
  coverpoint reg;
endgroup

In the example, you could see the usage of ‘option.comment’ feature. This way you can make the coverage group easier for the analysis.

2. Per Instance Coverage – ‘option.per_instance’

In your test bench, you might have instantiated coverage group multiple times. By default System, Verilog collects all the coverage data from all the instances. You might have more than one generator and they might generate different streams of transaction. In this case, you may want to see separate reports. Using this option you can keep track of coverage for each instance.

covergroup CoverPerInstance ;
  coverpoint tr.byte_cnt;
  option.per_instance = 1;
endgroup

3. Threshold using – ‘option.at_least’ 

This feature is useful when you don’t have sufficient visibility into the design to gather robust coverage. There might be cases where you just have information on a number of cycles that are needed for the transfers to cover required errors to get generated/simulated for defined cover point. Here you could set the option.at_least. For example, if we know that we need 10 cycles to cover this particular cover point, you could define option.at_leaset = 10.

4. Control on Empty bins – option.cross_num_print_missing = 1000

System Verilog coverage report by default shows only the bins with samples. But usually as a verification engineer, our job is to verify all cover points that are listed in the verification plan.

covergroup CoverCrossNumPrintMissing ;
	ByteCnt : coverpoint tr.byte_cnt;
	Length : coverpoint tr.length;
   option.cross_num_print_missing = 1000;
endgroup

5. Coverage Goal – option.goal

In system Verilog, the coverage goal for a cover group or point is the level at which the group or point is considered fully covered.

covergroup CoverGoal ;
    coverpoint tr.length;
    option.goal = 80;
endgroup

These are the few important coverage option features that are very useful in defining/coding System Verilog Functional Coverage.

About the author

The Art of Verification

Hi, I’m Hardik, and welcome to The Art of Verification.

I’m a Verification Engineer who loves to crack complex designs and here to help others commit to mastering Verification Skills through self-learning, System Verilog, UVM, and most important to develop that thought process that every verification engineer should have.

I’ve made it my mission to give back and serve others beyond myself.

I will NEVER settle for less than I can be, do, give, or create.

View all posts

2 Comments