Functional Coverage Guidelines for Implementers:

Functional coverage and code coverage both are contributing highly on sign off criteria for verification. Implementers have to make sure that their test plan and test environment is intelligent enough to satisfy the code/functional coverage closure. Code coverage is generated by tool with the help of the simulations generated by the test environment. So test environment should be random and intelligent enough to make sure design is covered as a part of code coverage and designer should be in agreement while code coverage review. There should be valid comments with reason for all exclusions for code coverage w.r.t to design specification. Functional coverage should be written in such a way that it should be able to capture all identified functionality while defining the test plan. Coverage and assertions are very important entity in the verification process and there are few guidelines that would help in verification process.

Few guidelines while working with functional coverage

  1. Your test plan should be based on the functionality you want to verify w.r.t to specification
  2. You should have a coverage matrix with the list of cover point details w.r.t to your test plan scenario and there should be a link of traceability between test scenario and cover point.
  3. Environment should have control mechanism for enabling or disabling coverage and assertions for better controllability in your environment
  4. Don’t enable functional coverage at the beginning of the verification to avoid simulation overhead in the starting phase of verification
  5. During the initial time of the verification bug ratio is typically higher, as you move forward to the verification bug ratio would start to drop. Here is the time when you should enable coverage and start analyzing it
  6. Functional coverage plan needs to be updated as verification progresses
  7. As your knowledge of the design and corner case understanding increases, you should keep updating your functional coverage plan
  8. Make effective use of cover group “trigger” and sampling mechanism.
  9. Follow meaningful names of cover group and cover points. This will help when you in debug process
  10. Coverage should not be captured on failing simulations. Make sure to gather coverage for only passing simulation. If few tests are not passing in regression first make sure to fix those issues before coming to a conclusion on coverage achievement
  11. If your tests are keep exercising the same logic in design, start developing the new tests for uncovered coverage part of coverage (coverage holes)

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The Art of Verification

Hi, I’m Hardik, and welcome to The Art of Verification.

I’m a Verification Engineer who loves to crack complex designs and here to help others commit to mastering Verification Skills through self-learning, System Verilog, UVM, and most important to develop that thought process that every verification engineer should have.

I’ve made it my mission to give back and serve others beyond myself.

I will NEVER settle for less than I can be, do, give, or create.

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