Concept of “This” in System Verilog:

Concept and usage of “this” is simple but important in test bench development using system verilog. I would like to share some insights on this concept.

The this keyword is an implicit argument to a method that refers to the current object. 

Let’s understand this concept with the following example.

class concept_this ;
  int a ;
  function new (int a);
    this.a = a;
  endfunction : new
program main;
  concept_this obj_th = new (777);
  initial begin
    $display ("obj_th.a = %d", obj_th.a);

In above example we can see that ‘a’ is a property of class “concept_this”. When we initialize the memory for class, we have passed an integer value ‘777’ to its class constructor i.e. function new(). The variable ‘a’ is local to class instance “obj_th and is now 777 as we have passed this from it’s class constructor.

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The Art of Verification

Hi, I’m Hardik, and welcome to The Art of Verification.

I’m a Verification Engineer who loves to crack complex designs and here to help others commit to mastering Verification Skills through self-learning, System Verilog, UVM, and most important to develop that thought process that every verification engineer should have.

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