The Art of Verification

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  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact

Category - UVM

  • UVM

How to Verify Complex RISC-V–based Designs?

September 23, 2022
by The Art of Verification
5 min read

As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or...

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  • System Verilog
  • UVM

Key Areas to consider during SOC Verification

January 12, 2022
by The Art of Verification
10 min read
4 Comments

Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two...

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  • UVM

How to handle Interrupt in UVM?

September 4, 2021
by The Art of Verification
6 min read

Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many IP blocks as part of it. In some way or other Interrupts are used to act as...

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  • UVM

How Virtual Interface can be pass using uvm_config_db in the UVM Environment?

September 2, 2021
by The Art of Verification
5 min read
7 Comments

How to connect the DUT to the UVM Testbench?? In our traditional directed Testbench environments, all the components are “static” in nature & information (data/control) is also exchanged in the form of...

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  • System Verilog
  • UVM

Clock Monitors in SoC Verification

August 5, 2021
by The Art of Verification
7 min read
6 Comments

Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors that use new bus architectures to communicate with them. They can also have various...

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  • UVM

How UVM RAL works?

July 5, 2021
by The Art of Verification
9 min read
12 Comments

Today let’s talk about UVM RAL. In this post, I will introduce – What is RAL? and Why RAL is needed? and How the UVM RAL structure looks like? We know that our DUT (be it an SoC or Subsystem or Design Block) contains a...

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  • System Verilog
  • UVM

SoC Verification Flow

June 5, 2021
by The Art of Verification
8 min read
2 Comments

Many people do not appreciate what makes a system-on-chip (SoC) different from other semiconductor devices. Many companies, especially in electronic design automation (EDA), toss around the term “SoC” without defining it or...

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  • UVM

How to Build UVM Environment Part – 4

May 16, 2021
by The Art of Verification
11 min read
5 Comments

Scoreboard The basic function of the scoreboard is to check the correctness of the output data of the design under test. The scoreboard you create should derive from uvm_scoreboard; however, there is no current functionality...

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  • UVM

How to Build UVM Environment Part – 3

May 16, 2021
by The Art of Verification
6 min read

AGENTS As mentioned, an agent is a container that instantiates the driver, monitor, and sequencer. Agents can be either active or passive. In active mode, all three components are created, while in passive mode only the...

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  • UVM

How to build UVM Environment Part – 2

May 16, 2021
by The Art of Verification
11 min read
1 Comment

SEQUENCER The job of the sequencer is to control the flow of sequences to the driver. The fact that you can write six lines of code yet have a powerful implementation is the beauty of UVM. Having the sequencer mechanism...

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Read More

  • Assertions and Advantages of Assertions
  • Concept of UVM Factory
  • Clock Monitors in SoC Verification
  • Advantages of UVM over SV
  • Immediate Vs Concurrent Assertions
  • Constraint Override in System Verilog:
  • @event Vs wait(event.triggered) in SystemVerilog
  • How to Verify Complex RISC-V–based Designs?
  • How to build UVM Environment Part – 2
  • UVM TLM Concepts:
  • Reset Testing using Phase Jump in UVM
  • M_sequencer Vs P_sequencer
  • Flavours of Fork..Join
  • How to think like a Verification Engineer
  • General Questions on Coverage:
  • Formal Verification: Where to use it and Why?
  • Logic in Systemverilog:
  • Streaming Operator in SystemVerilog(Pack/Unpack):
  • uvm_config_db and uvm_resource_db
  • Inheritance in SystemVerilog OOPs:
  • Virtual Vs Pure Virtual Methods:
  • Raise/Drop objection Automatically with UVM
  • Understanding with AXI Protocol and Cache Coherency
  • How to Build UVM Environment Part – 3
  • How to generate an array of unique random values
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  • Home
  • About
  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact
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  • Twitter
  • Google Plus