The Art of Verification

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  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact

Category - System Verilog

  • System Verilog
  • UVM

Key Areas to consider during SOC Verification

January 12, 2022
by The Art of Verification
10 min read
4 Comments

Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two...

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  • System Verilog
  • UVM

Clock Monitors in SoC Verification

August 5, 2021
by The Art of Verification
7 min read
6 Comments

Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors that use new bus architectures to communicate with them. They can also have various...

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  • System Verilog
  • UVM

SoC Verification Flow

June 5, 2021
by The Art of Verification
8 min read
2 Comments

Many people do not appreciate what makes a system-on-chip (SoC) different from other semiconductor devices. Many companies, especially in electronic design automation (EDA), toss around the term “SoC” without defining it or...

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  • System Verilog

Flavours of Fork..Join

March 24, 2021
by The Art of Verification
7 min read
8 Comments

Fork..Join: Fork…Join construct of System Verilog actually enables concurrent execution of each of its statements/threads/processes. This feature is most widely used for forking parallel processes/threads in System...

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  • System Verilog

Shallow Copy Vs Deep Copy

March 24, 2021
by The Art of Verification
4 min read
1 Comment

Shallow Copy: As we know that Classes contains Properties and Methods. A Class may also contain other Class Instantiation as a part of it. All these variables inside a Class got initialized once the Class is constructed. How...

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  • System Verilog

Concept of “This” in System Verilog:

March 24, 2021
by The Art of Verification
1 min read

Concept and usage of “this” is simple but important in test bench development using system verilog. I would like to share some insights on this concept. The this keyword is an implicit argument to a method that...

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  • System Verilog

Logic in Systemverilog:

March 24, 2021
by The Art of Verification
2 min read

Before we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”.  A wire is a data type that can model physical wires to connect two elements and It...

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  • System Verilog

“STATIC Properties and STATIC Methods”

March 24, 2021
by The Art of Verification
3 min read
2 Comments

STATIC Properties: As we know that in SystemVerilog Class Properties do not get created until the Object gets constructed. But there is an exception to that. When we add a “static” modifier to a Property that Property...

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  • System Verilog

STATIC and AUTOMATIC Lifetime:

March 24, 2021
by The Art of Verification
2 min read

Static: For a variable static lifetime is, its memory never de-allocated until simulation ends. Automatic: For a variable Automatic lifetime is, it is stack storage of variable (for multiple entries to a task, function, or...

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  • System Verilog

Why do we need a Virtual Interface?

March 24, 2021
by The Art of Verification
1 min read

This is a common interview question at an early stage of your career and an important one too. So, let’s understand why we need a virtual interface in our environment. Interface signals are static ( Physically available ) in...

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Read More

  • Different Array Types and Queues in System Verilog
  • Semaphore in SystemVerilog:
  • Functional Coverage Options in System Verilog
  • M_sequencer Vs P_sequencer
  • Logic in Systemverilog:
  • Mailbox in System Verilog
  • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
  • Typical UVM Testbench Architecture
  • Weighted Distribution in System Verilog
  • Generate randc behavior from rand variable:
  • System Verilog Assertion Binding (SVA Bind)
  • Polymorphism:
  • Constraint Override in System Verilog:
  • Encapsulation:
  • Inheritance in SystemVerilog OOPs:
  • @event Vs wait(event.triggered) in SystemVerilog
  • UVM Interview Questions
  • How to handle Interrupt in UVM?
  • Streaming Operator in SystemVerilog(Pack/Unpack):
  • Raise/Drop objection Automatically with UVM
  • Randcase Vs Randsequence in Systemverilog
  • UVM TLM Concepts:
  • Ifdef Vs plusargs:
  • How to build UVM Environment Part – 1
  • Virtual Vs Pure Virtual Methods:
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  • Home
  • About
  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact
  • Facebook
  • Twitter
  • Google Plus