The Art of Verification

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  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
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Category - Functional Coverage

  • Assertions
  • Functional Coverage
  • Interview Questions
  • System Verilog
  • UVM
  • Verification Fundamentals

Decoding the Art of Handling Clock Signals: Multiplication over Division

November 8, 2023
by The Art of Verification
3 min read

In the realm of digital design, clock signals play a pivotal role in synchronizing the operations of various components. While clock division is a common approach for generating clock signals with different frequencies, an...

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  • Assertions
  • Functional Coverage
  • System Verilog
  • UVM

Formal Verification vs Functional Verification: A Tale of Two Approaches

October 9, 2023
by The Art of Verification
3 min read

Formal verification and functional verification are two complementary approaches to ASIC verification. Formal verification uses mathematical methods to prove that a design meets its specifications, while functional verification...

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  • Assertions
  • Functional Coverage
  • System Verilog
  • UVM

Debugging is an Art, not a Science in Design Verification: Embracing the Human Touch

June 15, 2023
by The Art of Verification
4 min read

Introduction: In the realm of Design Verification, debugging stands as a crucial process for uncovering and rectifying issues that may compromise the functionality, reliability, and performance of complex chip designs. While the...

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  • Assertions
  • Functional Coverage
  • Interview Questions
  • System Verilog
  • UVM

🔍 Beyond Design: Why Thought Process Unlocks Verification Excellence 🔍

May 12, 2023
by The Art of Verification
3 min read
2 Comments

🌟 Hello Fellow Verification Engineers! 🌟 Let’s talk about the secret sauce that fuels verification excellence – the power of our thought process! As experts in our field, we understand that practical approaches...

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  • Functional Coverage
  • Interview Questions

General Questions on Coverage:

April 10, 2021
by The Art of Verification
13 min read
2 Comments

1. What is the difference between code coverage and functional coverage? There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification...

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  • Functional Coverage

Functional Coverage Guidelines for Implementers:

March 24, 2021
by The Art of Verification
2 min read
6 Comments

Functional coverage and code coverage both are contributing highly on sign off criteria for verification. Implementers have to make sure that their test plan and test environment is intelligent enough to satisfy the...

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  • Functional Coverage

Types of Coverage Metrics

March 24, 2021
by The Art of Verification
3 min read

Coverage is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality...

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  • Functional Coverage

Functional Coverage Options in System Verilog

March 24, 2021
by The Art of Verification
3 min read
2 Comments

Functional Coverage is very important in Test Bench Development. It always gives us confidence in covered items listed on the verification plan. Usually, the goal of a verification engineer is to ensure that the design behaves...

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Read More

  • Different Array Types and Queues in System Verilog
  • Generate randc behavior from rand variable:
  • Encapsulation:
  • Create() Vs new()
  • Functional Coverage Options in System Verilog
  • How to Build UVM Environment Part – 4
  • How to Build UVM Environment Part – 3
  • UVM Sequencer and Driver Communication:
  • UVM Macros, Messaging and UVM Reporting:
  • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
  • SoC Verification Flow
  • uvm_report_catcher/uvm_error demoter Example
  • uvm_config_db and uvm_resource_db
  • Advantages of UVM over SV
  • Formal Verification vs Functional Verification: A Tale of Two Approaches
  • How to generate an array of unique random values
  • randomize() Vs std::randomize()
  • Decoding the Art of Handling Clock Signals: Multiplication over Division
  • Formal Verification: Where to use it and Why?
  • System Verilog rand_mode() and constraint_mode()
  • How to handle Interrupt in UVM?
  • How UVM Phasing is triggered?
  • Ifdef Vs plusargs:
  • How to build UVM Environment Part – 1
  • Virtual Vs Pure Virtual Methods:
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  • Home
  • About
  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact
  • Facebook
  • Twitter
  • Google Plus