The Art of Verification

Creative ways to solve problems

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  • Home
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  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact

Author - The Art of Verification

  • Assertions
  • Functional Coverage
  • Interview Questions
  • System Verilog
  • UVM
  • Verification Fundamentals

Decoding the Art of Handling Clock Signals: Multiplication over Division

November 8, 2023
by The Art of Verification
3 min read

In the realm of digital design, clock signals play a pivotal role in synchronizing the operations of various components. While clock division is a common approach for generating clock signals with different frequencies, an...

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  • Assertions
  • Functional Coverage
  • System Verilog
  • UVM

Formal Verification vs Functional Verification: A Tale of Two Approaches

October 9, 2023
by The Art of Verification
3 min read

Formal verification and functional verification are two complementary approaches to ASIC verification. Formal verification uses mathematical methods to prove that a design meets its specifications, while functional verification...

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  • System Verilog
  • UVM
  • Verification Fundamentals

Unveiling the Masterpiece: The Art of Crafting an Unbeatable Verification Plan

August 9, 2023
by The Art of Verification
5 min read

As an experienced ASIC verification engineer, I’ve seen firsthand the importance of a thorough verification plan. A well-crafted verification plan can help to ensure that your design is bug-free and ready for production...

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  • Assertions
  • Functional Coverage
  • System Verilog
  • UVM

Debugging is an Art, not a Science in Design Verification: Embracing the Human Touch

June 15, 2023
by The Art of Verification
4 min read

Introduction: In the realm of Design Verification, debugging stands as a crucial process for uncovering and rectifying issues that may compromise the functionality, reliability, and performance of complex chip designs. While the...

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  • Assertions
  • Functional Coverage
  • Interview Questions
  • System Verilog
  • UVM

🔍 Beyond Design: Why Thought Process Unlocks Verification Excellence 🔍

May 12, 2023
by The Art of Verification
3 min read
2 Comments

🌟 Hello Fellow Verification Engineers! 🌟 Let’s talk about the secret sauce that fuels verification excellence – the power of our thought process! As experts in our field, we understand that practical approaches...

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  • System Verilog
  • UVM

Importance of Stress Verification !!

April 19, 2023
by The Art of Verification
3 min read

In the world of semiconductor design and verification, the Universal Verification Methodology (UVM) has become the industry standard for coverage-driven verification (CDV). CDV aims to ensure that all parts of a design are...

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  • System Verilog
  • UVM

How to approach solving complex issues?

April 7, 2023
by The Art of Verification
3 min read

As an engineer, debugging complex issues can be one of the most challenging tasks we face on a daily basis. When a problem arises, it can be tempting to jump in and start looking for the solution right away. However, taking a...

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  • UVM

How to Verify Complex RISC-V–based Designs?

September 23, 2022
by The Art of Verification
5 min read

As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or...

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  • Assertions

Formal Verification: Where to use it and Why?

May 5, 2022
by The Art of Verification
12 min read

With innovations in technologies and methodology, the benefits of formal functional verification apply in many more areas. If we understand the characteristics of areas with high formal applicability, we can identify not only...

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  • System Verilog
  • UVM

Key Areas to consider during SOC Verification

January 12, 2022
by The Art of Verification
10 min read
4 Comments

Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two...

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Read More

  • Flavours of Fork..Join
  • Decoding the Art of Handling Clock Signals: Multiplication over Division
  • @event Vs wait(event.triggered) in SystemVerilog
  • Encapsulation:
  • M_sequencer Vs P_sequencer
  • Semaphore in SystemVerilog:
  • randomize() Vs std::randomize()
  • System Verilog Assertion Binding (SVA Bind)
  • How UVM RAL works?
  • Constraint Override in System Verilog:
  • Streaming Operator in SystemVerilog(Pack/Unpack):
  • Enable/Disable specific constraints:
  • How to think like a Verification Engineer
  • Reset Testing using Phase Jump in UVM
  • UVM Sequencer and Driver Communication:
  • “STATIC Properties and STATIC Methods”
  • How to Build UVM Environment Part – 3
  • How to generate an array of unique random values
  • Generate the array of unique values without using random and constraints
  • uvm_config_db and uvm_resource_db
  • System Verilog Interview Questions
  • UVM TLM Concepts:
  • Basic Assertions Examples Part-2
  • Weighted Distribution in System Verilog
  • STATIC and AUTOMATIC Lifetime:
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  • Home
  • About
  • System Verilog
    • “STATIC Properties and STATIC Methods”
    • @event Vs wait(event.triggered) in SystemVerilog
    • Concept of “This” in System Verilog:
    • Constraint Override in System Verilog:
    • Different Array Types and Queues in System Verilog
    • Directed Testing Vs Constraint Random Verification
    • Enable/Disable specific constraints:
    • Inheritance in SystemVerilog OOPs:
    • Encapsulation:
    • Polymorphism:
    • Flavours of Fork..Join
    • Generate randc behavior from rand variable:
    • Generate the array of unique values without using random and constraints
    • How to generate an array of unique random values
    • Ifdef Vs plusargs:
    • Logic in Systemverilog:
    • Mailbox in System Verilog
    • Plusargs in SystemVerilog:
    • Randcase Vs Randsequence in Systemverilog
    • randomize() Vs std::randomize()
    • Semaphore in SystemVerilog:
    • Shallow Copy Vs Deep Copy
    • STATIC and AUTOMATIC Lifetime:
    • Streaming Operator in SystemVerilog(Pack/Unpack):
    • System Verilog rand_mode() and constraint_mode()
    • Virtual Vs Pure Virtual Methods:
    • Weighted Distribution in System Verilog
  • UVM
    • Advantages of UVM over SV
    • Callbacks Vs Factory
    • Clock Monitors in SoC Verification
    • SoC Verification Flow
    • Concept of UVM Factory
    • Create() Vs new()
    • Typical UVM Testbench Architecture
    • How to build UVM Environment Part – 1
    • How to build UVM Environment Part – 2
    • How to Build UVM Environment Part – 3
    • How to Build UVM Environment Part – 4
    • How to Terminate UVM Test? (UVM Objections)
    • How to handle Interrupt in UVM?
    • How UVM Callback works?
    • How UVM Phasing is triggered?
    • How UVM RAL works?
    • How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
    • M_sequencer Vs P_sequencer
    • Raise/Drop objection Automatically with UVM
    • Reset Testing using Phase Jump in UVM
    • UVM Macros, Messaging and UVM Reporting:
    • UVM Phasing
    • UVM Sequence Arbitration Mechanism
    • UVM Sequencer and Driver Communication:
    • UVM TLM Concepts:
    • uvm_config_db and uvm_resource_db
    • uvm_report_catcher/uvm_error demoter Example
    • Virtual Sequence and Sequencers:
    • Why do we need a Virtual Interface?
  • Functional Coverage
    • Types of Coverage Metrics
    • Functional Coverage Guidelines for Implementers:
    • Functional Coverage Options in System Verilog
  • Assertions
    • Assertions and Advantages of Assertions
    • Immediate Vs Concurrent Assertions
    • Basic Assertions Examples Part-1
    • Basic Assertions Examples Part-2
    • System Verilog Assertion Binding (SVA Bind)
  • Interview Questions
    • System Verilog Interview Questions
    • UVM Interview Questions
    • Understanding with AXI Protocol and Cache Coherency
    • General Questions on Coverage:
    • How to think like a Verification Engineer
  • BOOKS
  • Contact
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  • Twitter
  • Google Plus