Assertions and Advantages of Assertions

An assertion is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening in the design and occurs during simulation, then also the assertion fails.

Following are some of the advantages of using Assertions in Verification:

  • Assertions improve error detection in terms of catching simulation errors as soon a design specification is violated
  • Assertions provide better observability into the design and hence help in easier debug of test failures.
  • Assertions can be used for both dynamic simulations as well as in formal verification of design
  • Assertions can also be used to provide functional coverage on input stimulus and to validate that a design property is in fact simulated

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The Art of Verification

Hi, I’m Hardik, and welcome to The Art of Verification.

I’m a Verification Engineer who loves to crack complex designs and here to help others commit to mastering Verification Skills through self-learning, System Verilog, UVM, and most important to develop that thought process that every verification engineer should have.

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