The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of their SoCs. Quality is even more critical for highly configurable types of IP because...
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- STATIC and AUTOMATIC Lifetime:
- Basic Assertions Examples Part-1
- Understanding with AXI Protocol and Cache Coherency
- System Verilog Assertion Binding (SVA Bind)
- Directed Testing Vs Constraint Random Verification
- uvm_report_catcher/uvm_error demoter Example
- UVM Sequencer and Driver Communication:
- Immediate Vs Concurrent Assertions
- Key Areas to consider during SOC Verification
- Shallow Copy Vs Deep Copy
- Generate the array of unique values without using random and constraints
- How UVM Callback works?
- Clock Monitors in SoC Verification
- How to build UVM Environment Part – 1
- UVM Phasing
- General Questions on Coverage:
- How to Terminate UVM Test? (UVM Objections)
- SoC Verification Flow
- How to handle Interrupt in UVM?
- @event Vs wait(event.triggered) in SystemVerilog
- UVM Sequence Arbitration Mechanism
- uvm_config_db and uvm_resource_db
- Reset Testing using Phase Jump in UVM
- Different Array Types and Queues in System Verilog
- Inheritance in SystemVerilog OOPs: