September 2021 | The Art Of Verification

How to handle Interrupt in UVM?

Posted on September 4, 2021April 7, 2023 by The Art of Verification

Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many IP blocks as part of it. In some way or other Interrupts are used to act as the sideband signals of the Design/IP Blocks & most of the time it’s not the part of the main […]

How Virtual Interface can be pass using uvm_config_db in the UVM Environment?

Posted on September 2, 2021April 7, 2023 by The Art of Verification

How to connect the DUT to the UVM Testbench?? In our traditional directed Testbench environments, all the components are “static” in nature & information (data/control) is also exchanged in the form of signals/wire/nets at all levels in the DUT as well as in TestBench. But this is not the case in the latest “Constrained Random Verification Methodology” like […]