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The UVM sequence-driver API majorly uses blocking methods on sequencer and driver side as explained below for transferring a sequence item from sequencer to driver and collecting response back from driver. Sequencer side operations: There are two methods as follows: start_item(<item>): This requests the sequencer to have access to the driver for the sequence item […]
Continue ReadingVariable uvm_sequence_base::starting_phase is deprecated and replaced by two new methods set_starting_phase and get_starting_phase, which prevent starting_phase from being modified in the middle of a phase. This change is not backward-compatible with UVM 1.1, though variable starting_phase, although deprecated, has not yet been removed from the base class library. New method uvm_sequence_base::set_automatic_phase_objection causes raise_objection and drop_objection […]
Continue ReadingBefore we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”. A wire is a data type that can model physical wires to connect two elements and It should only be driven by continuous assignment statement and cannot hold any value if not driven. “Reg” in Verilog […]
Continue ReadingReset testing is a crucial element of functional sign-off for any chip. The architectural components of the entire verification environment need to be correctly synchronized to be made aware of the reset condition. Scoreboards, drivers and monitors need to be tidied up, and the complex stimulus generation needs to be killed gracefully. As we know, […]
Continue ReadingUVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology in terms of architecting testbenches and test cases, and also comes with a library of classes that helps in building efficient constrained random testbenches easily. Some of the advantages are listed below: Modularity and Reusability: […]
Continue ReadingToday I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively? Most UVM testbenches are composed of reusable verification components unless we are working on block-level verification of a simple protocol like MIPI-CSI. […]
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Introduction In the world of ASIC Verification, understanding the intricacies of various programming constructs is paramount. Today, we’ll delve deep into the concept of STATIC properties and STATIC methods in SystemVerilog, their significance, and their practical applications. 1. When to Use STATIC Properties and STATIC Methods STATIC properties are particularly useful when we need to share data across all […]
Continue ReadingStatic: For a variable static lifetime is, its memory never de-allocated until simulation ends. Automatic: For a variable Automatic lifetime is, it is stack storage of variable (for multiple entries to a task, function, or block, it will have stack storage) and its memory will be de-allocated once execution of that method or block is […]
Continue ReadingThis is a common interview question at an early stage of your career and an important one too. So, let’s understand why we need a virtual interface in our environment. Interface signals are static ( Physically available ) in nature where the Class-based environment is dynamic in nature So, A virtual interface is a pointer […]
Continue ReadingPolymorphism is the ability to have the same code act differently based on the type of Object that its being working with. This is a key topic of any Object Oriented Programming language. SystemVerilog enables Polymorphism in two ways: Dynamic (Run-Time) Static (Compile-Time) Here we’ll discuss the Dynamic mode of Polymorphism which is supported via “Virtual […]
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