Creative ways to solve problems
Factory stimulates everyone’s imagination to fall down on industrial settings and mechanical setup of machineries & processing units with products getting made and packaged before running on the transport rail & to be delivered to the warehouses. Hence the word “Factory” makes us curious to know about this jargon in Verification Methodology Context i.e. UVM. […]
Continue ReadingCallbacks and factory both addresses different areas of reusability in UVM. Callback: Add functionality to existing logic. Suitable for rare or minimal feature need to be enhanced in focus Popular for error injection/to corrupt the sequence from VIP. Easy to maintain callbacks Factory: It used to substitute the existing component before build, keeps environment same. […]
Continue ReadingCallback mechanism is used for altering the behavior of the transactor/BFM without modifying the existing BFM/transactor. Callback gives flexibility to plug-and-play and reuse the components i.e. driver, monitor etc.. Sometimes requirements are often unpredictable when the BFM/transactor is first written. So a transactor should provide some kind of hooks for executing the code which is […]
Continue ReadingM_sequencer: When a sequence is started, it is always associated with a sequencer on which it is started. The m_sequencer handle contains the reference to the sequencer on which sequence is running. Using this handle, the sequence can access any information and other resource handles in the UVM component hierarchy. P_sequencer and how it is […]
Continue Readinguvm_resource_db: uvm_resource_db is base class and uvm_config_db is extended from uvm_resource_db. Using the resource_db requires that the scope (arbitrary string) for the set and get a match. For trivial environments, this isn’t difficult. However, for complex environments, including IP from different sources, it’s more difficult to manage. That, along with some other non-intuitive behaviors of […]
Continue ReadingFork..Join: Fork…Join construct of System Verilog actually enables concurrent execution of each of its statements/threads/processes. This feature is most widely used for forking parallel processes/threads in System Verilog Test Benches. System Verilog came up with new and advanced flavors of fork join construct which adds a lot of value for implementers. Fork..Join_any Fork..Join_none Let’s start […]
Continue ReadingMultiple sequences can interact concurrently with a driver connected to a single interface. The sequencer supports an arbitration mechanism to ensure that at any point of time only one sequence has access to the driver. The choice of which sequence can send a sequence_item is dependent on a user selectable sequencer arbitration algorithm. There are […]
Continue ReadingIntroduction: It is necessary to manage most of the verification tasks, such as generating stimulus and collecting coverage data, at the transaction level, which is the natural way of verification engineers tend to think of the activity of a system. UVM provides a set of transaction-level communication interfaces and channels that you can use to […]
Continue ReadingShallow Copy: As we know that Classes contains Properties and Methods. A Class may also contain other Class Instantiation as a part of it. All these variables inside a Class got initialized once the Class is constructed. How does that happen, lets see using the following example: Here we are having two Classes named “Class […]
Continue ReadingConcept and usage of “this” is simple but important in test bench development using system verilog. I would like to share some insights on this concept. The this keyword is an implicit argument to a method that refers to the current object. Let’s understand this concept with the following example. In above example we can […]
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